ChipsDan Luualmost 13 years ago
Writing safe Verilog
6 min read
A team of formal methods PhDs built a linter that typechecks Verilog code based on naming conventions. The linter catches pipeline stage mismatches and cross-clock-domain errors in seconds, preventing bugs that take hours of waveform tracing to find. Unsynchronized clock domain crossings can burn massive power.
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