HardwareHacker Newsabout 3 hours ago
The Anatomy of an Instruction Pipeline Hazard
1 min read
An engineer discovered a silent correctness bug in the Nvidia B200 GPU where a compiler scheduler missed a predicate dependency between ISETP and BRA instructions. Microbenchmarking on actual silicon revealed the physical predicate latency floor is approximately 4 cycles, diverging from the modeled 13 cycles. Fixed-latency arithmetic instructions like FFMA require precise stall cycles to avoid stale register reads.
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