Synopsys 3D PCIe 6.0 PHY hits 64 GT/s

Synopsys validated a 5nm PCIe 6.0 PHY in a face-to-face 3D stack running 64 GT/s per lane and 128 GB/s across eight lanes with PAM4 signaling. The company modified an existing 2D test chip with through-silicon vias and 3D process design kits.